Project : dart

Section: Contracts and Grants with Industry

SoCLib RNRT Platform Project

Partners:

CEA, CNRS, Thales Communications, ST Microelectronics, Prosilog, TurboConcept.

This project consists to develop an integration platform for a fast and secure SoC Design from IPs. Models of hardware components have to be interoperable, validated and available at different levels of abstraction

The DaRT team participates to this effort via the CNRS SoCLib ``equipe-projet''. Our contribution concerns the optimisation of the SystemC runtime. We propose adapters for interoperability.